View LC8904Q_1263945.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Ordering number : EN*5014B
CMOS LSI
LC8904Q
Digital Audio Interface Receiver
Preliminary Overview
The LC8904Q demodulates data transmitted between digital audio equipment in the EIAJ format (CP-1201) to a normal format signal synchronized with the receiving side input signal.
Package Dimensions
unit: mm 3156-QFP48E
[LC8904Q]
Features
* Synchronizes with the transmitted EIAJ format signal using a built-in PLL circuit. * Modes are set up and codes are output according to commands sent over a microprocessor interface. -- Input pin and output data format setup -- Selection of digital source mode or analog source mode -- 32-bit channel status output (consumer product mode 0) -- 80-bit subcode Q data output (CRC check included) * Either a 384fs or a 512fs clock can be selected as the system clock. * Provides 256fs, 128fs, BCLK, and LRCK clock outputs. * Implements a CD subcode interface (CP-2401) using user bits. * Fabricated in a CMOS single-voltage power supply process * Package: QFP-48E
SANYO: QIP48E
* CCB is a trademark of SANYO ELECTRIC CO., LTD. * CCB is SANYO's original bus format and all the bus addresses are controlled by SANYO.
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-0005 JAPAN
73096HA (OT) No. 5014-1/20
LC8904Q Pin Assignment
No. 5014-2/20
LC8904Q Block Diagram
No. 5014-3/20
LC8904Q Pin Functions
No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Symbol DOUT/V EMPHA RC1 RC2 CCB/SUB DGND CLKMD CLK TEST1 TEST2 XMODE DVDD NC AVDD R AGND VIN VCO DVDD SBSY PW SFSY SBCK DGND DVDD XIN XOUT CLKOUT1 CLKOUT2 ERROR DGND SUB1 SUB2 BCLK DATAOUT LRCK LD/DQSY SRDT DO DI/SWDT CE/XLAT CL/SCLK DVDD DIN1 DIN2 DIN3 DIN4 DGND I I I I O O O O O O O O I I I I O O O O O O O I I O I I I I I I I/O O O I O I EIAJ data and validity flag output Emphasis monitor output (High: emphasis applied) CR oscillator input CR oscillator output Microprocessor interface selection input (High: CCB, low: SUB) Digital system ground Clock output switching (High: 256fs, low: 128fs) Clock switching input (High: 512fs, low: 384fs) Test pin (Must be tied low during normal operation.) Test pin (Must be tied low during normal operation.) Reset input Digital system power supply No connection Analog system power supply VCO oscillator band adjustment input Analog system ground VCO free-running frequency setting input PLL low-pass filter connection Digital system power supply CD subcode interface: block sync output CD subcode interface: data output CD subcode interface: frame sync output CD subcode interface: data read shift clock input Digital system ground Digital system power supply Crystal oscillator input Crystal oscillator output VCO and crystal oscillator clock output 256fs or 128fs clock output (selected by CLKMD) Error mute output Digital system ground Sampling frequency monitor output Sampling frequency monitor output Bit clock output Audio data output L/R clock output (High: left channel, low: right channel) Microprocessor interface: subcode Q data sync output Microprocessor interface: data output when CCB/SUB is low (3-state output) Microprocessor interface: data output when CCB/SUB is high (High-level open drain output) Microprocessor interface: data input Microprocessor interface: chip enable/latch input Microprocessor interface: clock input Digital system power supply Data input with built-in amplifier Data input with built-in amplifier Data input with built-in amplifier Data input with built-in amplifier Digital system ground Function
No. 5014-4/20
LC8904Q
Specifications
Absolute Maximum Ratings at Ta = 25C
Parameter Maximum supply voltage Input and output voltage Operating temperature Storage temperature Symbol VDD max VI * VO Topr Tstg Conditions Ratings -0.3 to +7.0 -0.3 to VDD + 0.3 -30 to +75 -55 to +125 Unit V V C C
Allowable Operating Ranges
Parameter Supply voltage Symbol VDD Conditions min 4.5 typ 5.0 max 5.5 Unit V
Electrical Characteristics DC Characteristics at Ta = -30 to +75C, VDD = 4.5 to 5.5 V
Parameter Input high-level voltage Input low-level voltage Input high-level voltage Input low-level voltage Input high-level voltage Input low-level voltage Output high-level voltage Output low-level voltage Current drain Input amplitude Note: 1. 2. 3. 4. 5. Symbol VIH1 VIL1 VIH2 VIL2 VIH3 VIL3 VOH VOL IDD VPP *1 *1 *2 *2 *3 *3 IOH = -1 A IOL = 1 A *4 *5 0.4 30 Conditions min 2.2 -0.3 0.7 VDD -0.3 0.8 VDD -0.3 VDD - 0.05 VSS + 0.05 45 VDD + 0.3 typ max VDD + 0.3 +0.8 VDD + 0.3 0.3 VDD VDD + 0.3 0.2 VDD Unit V V V V V V V V mA V
Input pins other than DIN1, DIN2, DIN3, DIN4, RC1, and XMODE. TTL compatible. The XIN pin. CMOS compatible. The XMODE and RC1 pins. CMOS Schmitt compatible. VDD = 5.0 V, Ta = 25C, and input data with an fs of 48 kHz. Conditions prior to the capacitances of the DIN1, DIN2, DIN3, and DIN4 pins.
No. 5014-5/20
LC8904Q AC Characteristics at Ta = -30 to +75C, VDD = 4.5 to 5.5 V
Parameter Output pulse width Output data setup time Output data hold time Symbol tWBO tDSO tDHO Conditions fs = 48 kHz, load = 30 pF fs = 48 kHz, load = 30 pF fs = 48 kHz, load = 30 pF min 160 80 80 typ max Unit ns ns ns
Note: When the validity fag is output from the DOUT/V pin.
No. 5014-6/20
LC8904Q Microprocessor Interface AC Characteristics (when CCB/SUB is low) at Ta = -30 to +75C, VDD = 4.5 to 5.5 V
Parameter SCLK low-level pulse width SCLK high-level pulse width Setup time Hold time Delay time Latch pulse time DQSY pulse time Data delay time Data delay time Symbol tWL tWH tDS tDH tD tWLA tW tD1 tD2 fs = 44.1 kHz CL = 30 pF CL = 30 pF Conditions min 100 100 50 50 100 100 136 75 75 typ max Unit ns ns ns ns ns ns s ns ns
No. 5014-7/20
LC8904Q Microprocessor Interface AC Characteristics (when CCB/SUB is high) at Ta = -30 to +75C, VDD = 4.5 to 5.5 V
Parameter CL low-level pulse width CL high-level pulse width Data setup time Data hold time CE delay time CL delay time CE delay time LD pulse time Data delay time Data delay time Symbol tWL tWH tDS tDH tD3 tD4 tD5 tW tD1 tD2 fs = 44.1 kHz CL = 30 pF CL = 30 pF 136 75 75 Conditions min 100 100 50 50 1.0 50 100 typ max Unit ns ns ns ns s ns ns s ns ns
Note 1. C bit output 2. Subcode Q output
No. 5014-8/20
LC8904Q CD Subcode Interface AC Characteristics at Ta = -30 to +75C, VDD = 4.5 to 5.5 V
Parameter SBSY block period SBSY pulse width SFSY frame period SFSY high-level pulse width SFSY low-level pulse width SBCK high-level pulse width SBCK low-level pulse width SBCK rise time SBCK fall time SBCK delay time P data access time Data hold time Symbol tB tBW tF tFHW tFLW tCHW tCLW trC tfC tCD tPAC tHD 0 *3 10 20 3 *3 *3 *1 *2 Conditions min 12.0 110 90 4 1.5 2.0 2.0 4.0 4.0 5.0 5.0 30 30 30 10 136 165 typ 13.3 max 14.7 Unit ms s s s s s s ns ns s s s
No. 5014-9/20
LC8904Q The LC8904Q subcode interface uses the user bit subcode sync word and start bit for system timing extraction. Therefore, since SBSY and SFSY will change with that timing, user bit transmission must follow the table shown below when using the values of tBW, tF, tCHW, tCLW, and tCD with the specifications listed in the preceding tables.
Note: 1. The subcode sync word is defined as the block sync section (block start) when 0-valued data has been received consecutively for at least 22 bits. 2. The period of the frame sync signal S0 is 90.7 s. The S1 period also has a minimum length of 90.7 s (when 0-valued data is received consecutively for 22 bits), depending on the subcode sync word period. Not that the shortest word is 10 bits. 3. The SBCK signal input delay (tHD) and pulse widths (tCHW and tCLW) must be set to values less than or equal to the typical values when the shortest user data word length is used.
No. 5014-10/20
Microprocessor Interface
1. When CCB/SUB is low
LC8904Q
No. 5014-11/20
2. When CCB/SUB is high
LC8904Q
No. 5014-12/20
LC8904Q The microprocessor interface controls the following settings and outputs. 1. 2. 3. 4. 5. 6. 7. System stop Data input pin settings Validity flag (V flag) output selection Analog source mode setting Output data format setting Channel status (32 bits) output Output of the 80-bit subcode Q data with CRC flags. * CCB/SUB pin The CCB/SUB pin selects one of two formats. The clocks and codes must be set up appropriately for each of these formats. SRDT is the output pin when CCB/SUB is low. SRDT goes to the high-impedance state when the CCB/SUB pin is high, during writes, and when an address for a different output is latched. In contrast with the SRT pin, the DO pin is a high-level open drain output that functions as the output pin when CCB/SUB is high. * Data I/O address Address are allocated according to the differing formats as listed below.
Format I/O Data input Data output (C bits) Data output (subcode Q) EA E9 E8 B0 0 1 0 B1 1 0 0 CCB/SUB = low B2 0 0 0 B3 1 1 1 A0 0 0 0 A1 1 1 1 A2 1 1 1 A3 1 1 1 F7 F8 F9 B0 1 0 1 B1 1 0 0 CCB/SUB = high B2 1 0 0 B3 0 1 1 A0 1 1 1 A1 1 1 1 A2 1 1 1 A3 1 1 1
* Input The DIN1 to DIN4 data input pins have built-in amplifiers, and can accept signals with amplitudes of about 400 Vp-p. Note that the DOUT pin can be set up to output the EIAJ format data by microprocessor interface commands. (It can also be used to output the V flag.)
* Input code settings System stop by stopping both the VCO and crystal oscillators (DI4)
DI4 System L Run H Stop
Selection of data to demodulate (DI5, DI6)
DI5 DI6 Demodulation data input L L DIN1 H L DIN2 L H DIN3 H H DIN4
Input data (EIAJ format) output selection
DI7 DI8 DOUT/V pin L L DIN1 H L DIN2 L H DIN3 H H DIN4
No. 5014-13/20
LC8904Q V flag output selection (DI9)
DI9 DOUT/V pin L Data selected by DI7 and DI8 H V flag
Source selection (DI10)
DI10 Mode L Digital source H Analog source
Audio data output format setting (DI11, DI12, DI13)
DI11 DI12 DI13 DATAOUT L L L 16 bits MSB first Rear packed L L H 16 bits MSB first Front packed H L L 20 bits MSB first Rear packed H H L 20 bits LSB first Rear packed H L H 20 bits MSB first Front packed H H H 20 bits LSB first Front packed
DI4 to DI13 are set to an initial value of low, immediately after the XMODE pin goes from low to high. Since DI0 to DI3 and DI14 to DI15 are unused they can be set to either low or high. * Output C bits -- This product only supports 32 bits, since it is designed for mode 0 consumer applications. -- In readout when CCB/SUB is low, after the output address is loaded into SWDT, the flag (fixed at the high level) is output on the fall of XLAT, and then 32 bits of data is output according to SCLK. -- In readout when CCB/SUB is high, after the output address is loaded into DI, the 32 bits of data are output from DO according to CL while CE is high. -- Since the C bits are not checked for errors, processing is performed after the PLL lock state is detected. Therefore, data must be read out only after the ERROR pin goes low. -- If a lock error occurs during readout (ERROR = high), the shift register will be reset and all data will become 0 (low). However, while the ERROR pin will also go high on a parity error, this error processing will not be performed. -- An interval of at least 6 ms or longer must be provided between readout operations. Subcode Q -- The LC8904Q provides the following two functions for subcode readout: 1. CD subcode interface (CP-2401) is possible 2. Output of subcode Q data with CRC flags included, which corresponds to the CD and MD formats The microprocessor interface uses the readout function of item 2. -- The subcode Q data, which is reproduced at 1 bit per frame, is input to an 80-bit register and a CRC checking circuit. After the 96 bits of data have been input, it is loaded into a shift register on the falling edge of LD/DQSY. The data must be read out after this load operation. -- In readout when CCB/SUB is low, after the output address has been loaded into SWDT, the CRC flags are output on the falling edge of XLAT. If the CRC flags indicate that the check was OK, a high level is output. Next, 80 bits of data is output from SRDT according to SCLK. Note that the subcode Q data is updated on every falling edge of the DQSY signal. -- Readout when CCB/SUB is high is identical to that described in item 3. (See the timing charts for details.) -- The data output from SRDT (DO) has the same order on a per-byte basis, but the bit order within each byte is LSB first. -- If a lock error occurs between the fall of DQSY and the fall of XLAT, the CRC flags will go low. However, if a lock error after the fall of XLAT, the CRC flags will not go low, since correct data will be output.
No. 5014-14/20
LC8904Q -- When the 96 bits of the subcode Q data have been read in with the PLL circuit in the locked state, a sync signal that has a low period with a pulse width of 136 s is output by outputting at least 22 bits of continuous 0-valued data after the 96 bits of W data (W97) from DQSY. Note that this sync signal low-level pulse will not be output unless 96 bits of subcode Q data including the CRC flags are input.
When not Using the Microprocessor Interface If the LC8904Q is used without using the microprocessor interface, the microprocessor interface pins must be tied to fixed levels and data only input to pin DIN1. This configuration can be useful as a simplified circuit evaluation method. CD Subcode Interface The LC8904Q outputs CD subcode data from the SFSY, SBCK, PW, and SBSY pins. These pins output user bits that were transmitted according to the CP-1201 standard and that were converted to the CP-2401 standard.
The timing of the rise and fall of the SFSY signal is converted into that shown in the figure below according to the timing of the start bit in the user bits in the input data.
No. 5014-15/20
LC8904Q The CLK, CLKMD, CLKOUT1, and CLKOUT2 Pins The output clocks for the CLKOUT1 and CLKOUT2 clock output pins is selected by the CLK and CLKMD pins.
CLK L H CLKOUT*1 Outputs a 384fs clock Outputs a 512fs clock CLKMD L H CLKOUT2 Outputs a 256fs clock*2 Outputs a 128fs clock
Note: 1. The crystal oscillator clock is output in analog source mode. 2. The 256fs clock has a H:L duty ratio of 2:1 when the CLK pin is low.
The SUB1 and SUB2 Pins These pins indicate the sampling frequency of the input data.
Pin SUB1 SUB2 32 kHz H H 44.1 kHz L L 48 kHz L H #1 H L
The state "#1" is indicated on a PLL lock error and in analog source mode. Also note that the DATAOUT and EMPHA pins will output low levels in this state. The EMPHA Pin
Pin EMPHA Emphasis applied H Emphasis not applied L Analog source mode L
The ERROR pin and Error Processing ERROR pin: When an error exists in the input data or when the PLL circuit is in the unlocked state, this pin goes high and holds that high level for about 200 to 300 ms after data demodulation returns to normal. The table below lists the data processing applied when an error occurs.
Type of error Up to eight consecutive parity errors Eight or more consecutive parity errors PLL lock error DATAOUT Previous data L L SUB1, SUB2 Output Output #1 C bit Output Output L Sub Q* Output Output L
Note: * The CRC flags go low when a PLL lock error occurs. Note: PLL lock error determination is performed starting from preamble detection.
The XMODE Pin This pin is used for system reset. The system will start to operate normally if this pin is set high after the power supply has risen to at least 4.5 V. If XMODE is set low, the VCO free-running clock will be output from the CLKOUT1 pin.
After application of power, the system will be reset if the XMODE pin is set low again.
No. 5014-16/20
LC8904Q Analog Source Mode The LC8904Q enters analog source mode in the following two cases: 1. Analog source mode is selected from the microprocessor interface. 2. If the input pin specified for data demodulation goes to the no signal state. In this mode, the clock that operates the whole system is taken from the crystal oscillator clock, and the PLL and data demodulation circuits are stopped. The BCLK, LRCK, CLKOUT1, and CLKOUT2 clocks are output. The output pins have the following functions in analog source mode: 1. DOUT/V Data output as specified by the microprocessor interface 2. ERROR Outputs the error state, i.e. a high level. 3. SUB1 and SUB2 These pins output the "#1" lock error state. 4. DATAOUT Outputs the lock error state, i.e., a low level. 5. EMPHA Outputs the lock error state, i.e., a low level. 6. Microprocessor interface codes Input codes: The codes loaded from the microprocessor interface are retained. Output codes: The same codes as output for a PLL lock error. Crystal Oscillator 1. A built-in detector circuit determines whether or not a data input signal is present. This circuit operates from either the VCO or the crystal oscillator clock. When the power supply is coming up, this clock is supplied from the VCO, and if a no-data state is detected, the system switches to the crystal oscillator clock. Here, if the clock is not supplied from the crystal oscillator after a no-data state is detected, the whole system goes to the stopped state, and, since the detector circuit does not operate even if data is supplied, the system will remain in the stopped state. 2. The XIN and XOUT pins include a built-in oscillator amplifier circuit, and operate as follows when a crystal oscillator element is attached.
Pin XIN XOUT Data present* H L No data Crystal oscillator input accepted Outputs the inverse of the XIN pin state.
Note: * When data is present, the XIN pin is pulled up internally.
Data Output Timing 1. Data is output in synchronization with the falling edge of the BCLK signal. 2. Data, BCLK, and LRCK are output in synchronization with the rising edge of the 256fs clock. 3. The figure on the following page shows the data output timing.
No. 5014-17/20
LC8904Q
Data Output Timing
No. 5014-18/20
LC8904Q Application Circuit Example
No. 5014-19/20
LC8904Q
s No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. s Anyone purchasing any products described or contained herein for an above-mentioned use shall: Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. s Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of July, 1996. Specifications and information herein are subject to change without notice. PS No. 5014-20/20

▲Up To Search▲

Price & Availability of LC8904Q

	To Download LC8904Q Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .